WLWooram Lee 

Ph.D. Candidate, Cornell University

Email: wl287(at)cornell.edu

Address: 362 Duffield Hall, Cornell University, Ithaca, NY 14853

Phone: 607-227-3943

Link to Wooram's CV

Wooram Lee received his B.Sc. and M.S. degrees in Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea in 2001 and 2003, respectively, and  he is currently working toward his Ph.D. degree at Cornell University, Ithaca, NY.  

He has held a summer internship at the IBM  T.J. Watson Research Center in Yorktown Heights, NY, in 2011, where he worked on a millimeter-wave frequency multiplier in a 90 nm SiGe process. Before joining Cornell, he was a research engineer at the Electronics and Telecommunications Research Institute (ETRI), Daejeon, Korea, where he worked on optical transceivers and links from 2003 to 2007.  His research interests include high performance RF IC design, exploiting nonlinear electronics for signal generation and processing in very high frequency and low noise applications.

Awards and Honors

Research ProjectswL

Noise squeezing beyond the thermal noise limit

To achieve sensitivity below the thermal noise limit, we demonstrated noise squeezing in electrical circuits for the first time. This concept was originally studied in optics to achieve sensitivity below the limit of the uncertainty principle. We found that we can enhance the sensitivity of one signal aspect (e.g., the phase of in-phase components) at the expense of degrading the other orthogonal aspect (e.g. the amplitude, or quadrature component). The first prototype was a 10-GHz CMOS low-noise amplifier with a sensitivity enhancement factor of 2.5 dB for one quadrature phase. (TCAS2011, MTT2012) Moving forward, we are working on a system of coupled oscillators that can enhance the phase noise by exploiting the noise squeezing effect. 







Electrical parametric oscillator: the first passive CMOS frequency divider

To reduce overall system power and phase noise in high-speed frequency synthesizers, we propose an electrical distributed parametric oscillator to realize a passive CMOS frequency divider. Instead of using active devices, which are the main sources of noise and power consumption, an oscillation at half of the input frequency is sustained by the parametric process based on nonlinear interaction with the input signal. To show the feasibility of the proposed approach, we have implemented a 20-GHz frequency divider in a 0.13-um CMOS process. To the best of our knowledge, this is the first passive frequency divider in a CMOS process. (JSSC 2010)            



Nonlinear lattice for high-amplitude picosecond pulse generation in CMOS

To go beyond the transistor limits in sharp pulse generation, we use nonlinear wave interaction in a two-dimensional electrical medium. In this system, when two waves collide orthogonally, they combine in a nonlinear fashion: The amplitude of the outgoing wave is greater than the sum of the incoming waves with much higher frequency components. The key is that nonlinearity localizes energy in time and space, resulting in high-amplitude, narrow pulses at the output. After analyzing this concept, we demonstrated 2.7-V pulse generation with a 6-ps pulse width from a 22-GHz input. To the best of our knowledge, regarding the high-amplitude pulses, this work shows the sharpest pulse in any CMOS process. (MTT2012, JPA2010, MTT 2010)                     


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